TOP > ICE Cube Center

ICE Cube Center

	Prof. Takayuki OHBA （Specially Appointed）
	Room: J3	Mail-Box: J3-132
	TEL: 045-924-5866
	E-mail: ohba.t.ac(at)m.titech.ac.jp Please replace “(at)” with “@”.
	HomePage:http://www.wow.pi.titech.ac.jp/

Research Field　BBCube LSI Semiconductor Process Development and Applications
Objective　To develop the cutting-edge BBCube three-dimensional large-scale integration technology and drive the semiconductor industry beyond scaling.
Current Topics
・Development of mass-production-ready WOW/COW processes, equipment, and materials.
・BBCube 2.5D/3D system development.
・BBCube thermal design and heat dissipation technology development.
・Wide-bandgap materials research.
・Social implementation through the WOW Alliance.


	Bumpless vertical interconnects between wafers

	Prof. Norio CHUJO （Specially Appointed）
	居室: R2棟	Mail-Box: R2-32
	TEL: 045-924-5083
	E-mail: chujou.n.253b(at)m.isct.ac.jp Please replace “(at)” with “@”.
	HomePage: http://www.wow.pi.titech.ac.jp/

Research Field　Design and architecture of BBCube 3D integration
Objective　Development of semiconductor technologies that achieve both high performance and low.
Current Topics
・Research and development of BBCube 3D systems stacking xPUs (e.g., CPUs and GPUs), memory, and voltage regulators
・Development of low-power, high-bandwidth inter-chip communication technologies for 2.5D/3D integration
・Development of vertically integrated high-efficiency power delivery solutions
・Advanced thermal design and heat dissipation technology development

BBCube 3D configuration
・Multi-xPU/IVR/Multi-Memory Vertical Stack
・WOW and COW Hybrid Processes
・Cu-Damascene Via-Last TSVs)

	Prof. Shiro DOSHO（Specially Appointed）〔Ito Lab〕
	Room: J2	Mail-Box: J2-31
	TEL: 045-924-5019
	E-mail: dosho.s.aa(at)m.titech.ac.jp Please replace “(at)” with “@”.
	HomePage: http://www.ateal.first.iir.titech.ac.jp/

	Prof. Tomoji NAKAMURA（Specially Appointed）〔Ito Lab〕
	Room: R2	Mail-Box: R2-32
	TEL: 045-924-5083
	E-mail: nakamura.t.bh(at)m.titech.ac.jp *Please replace “(at)” with “@”.
	HomePage:

Research Field　Heat exchange and heat transport technologies in electronic products
Objective　Improve cooling efficiency of the overall system by dispersing, transporting, and exchanging heat generated by electronic products using gas-liquid two-phase flow.
Current Topics
・Development of cooling devices that disperse, transport, and exchanging heat generated by electronic devices with high power consumption using gas-liquid two-phase flow.
・Computational Fluid Dynamics simulation for 2-phase flow that covers evaporation, transport, and coagulation of water in an integrated manner.

Schematic cross section of vapor chamber (VC)

Heat transfer performance of the prototype VC

	Prof. Katsuyuki MACHIDA（Specially Appointed）〔Ito Lab〕
	Room：J2	Mail-Box：J2-31
	TEL：045-924-5019
	E-mail：machida.k.ad(at)m.titech.ac.jp Please replace “(at)” with “@”.

Research Field　Integrated CMOS-MEMS Technology for high performance of a function device.
Objective　In order to realize the integration, we have developed and researched the each technology such as MEMS, LSI circuit, packaging, and design technologies.
Current Topics
・High sensitive CMOS-MEMS accelerometer

SEM and optical photographs of CMOS-MEMS accelerometer

	Prof. Takashi YODA（Specially Appointed）〔Ohba Lab〕
	Room: R2	Mail-Box: R2-32
	TEL: 045-924-5083
	E-mail: yoda.t.ab(at)m.titech.ac.jp Please replace “(at)” with “@”.
	HomePage: http://www.wow.pi.titech.ac.jp/

Research Field 　Wide Band Gap (WBG) Semiconductor Technology
Objective 　Development of the High performance SiC/(GaN) devices
Current Topics
・Defect-Free Engineering
– Lifetime Measurement
– Dislocation Modeling
・Diagnotics Technology
・Advanced Application of WBG Devices


Lifetime measurement for n-Buffer SiC layer	Hyperspectral Raman Imaging of 4H-SiC BPD

	Prof. Kuan-Neng CHEN（Specially Appointed）〔Ito Lab〕
	Room：J3	Mail-Box：J3-132
	TEL：045-924-5866
	E-mail: chen.k.af(at)m.titech.ac.jp Please replace “(at)” with “@”.
	HomePage:

	Prof. Young Suk KIM （Visiting）〔Ito Lab〕
	Room：J3	Mail-Box：J3-132
	TEL：045-924-5866
	E-mail：youngsuk.k.aa(at)m.titech.ac.jp Please replace “(at)” with “@”.
	HomePage: http://www.wow.pi.titech.ac.jp/

Research Field　Process Integration Development for 3D LSI Devices
Objective　To develop ultra-thinning of 300-mm device wafers and those stack process integration
technology for three-dimensional LSI technology. Because the physical interconnects length becomes 1/10 using ultra-thin wafers and Wafer-on-Wafer (WOW) process, high performance 3D devices with low power consumption will be realized.
Current Topics
・Ultra-thinning 300-mm DRAM wafer down to 2-μm
・Bumpless vertical interconnects between wafers
・Analyses of defect generation and device characteristics for thinned device wafer

Thinned DRAM 300mm wafer